This invention relates to improvements in floating point multiply operations, and more particularly, in one embodiment, to a method for calculating the "sticky bit" in a floating point multiply by utilizing existing normalization and alignment circuitry which is used in floating point add/subtract operations.
A floating point multiply of two n-bit operands creates a 2n-bit result, but only an n-bit result is usually required. Thus, the 2n-bit result is rounded to n-bits in a floating point processor. Some rounding algorithms, for example the "round to nearest/even" algorithm (required by IEEE standard 754-1985), require knowledge of the presence of any "1" in the n-2 low-order bits of the 2n-bit result. The presence of any such "1" causes a so-called "sticky bit" to be set (i.e., set to "1").
Array type multipliers are used in floating point processors of the single-chip type to accelerate the floating point multiply operation. An array multiplier can produce a result in one or two clock cycles, whereas a more conventional multiply implemented by add and shift operations can occupy dozens of clock cycles. Generally, an array multiplier produces the result as two vectors, a sum vector and a carry vector. The vectors must be added in a carry propagate adder to produce the n-bit result. For correct rounding, a carry-out must be generated from the carry-propagate of the low-order n-2 bits. The n-bit final result will not include the sum bits of the low-order n-2 bit addition, and therefore generating these sums constitutes a costly overhead both in terms of speed and chip area. The low-order n-2 bit carry-out, in conjunction with the sticky bit, is used to correctly round the n-bit result.
An observation by Santoro et al in "Rounding Algorithms for IEEE Multipliers," Proc. Ninth IEEE Symposium on Computer Arithmetic, p. 176-183, 1989, suggests computing the sum of trailing zero's in the multiplier and multiplicand, so if the sum is n-2 or larger, then the sticky bit will not be set.